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SPT9110 100 msps single-to-differential track-and-hold applications ? tha for differential adcs ? rf demodulation systems ? test instrumentation ? digital sampling oscilloscopes features ? 400 mhz sampling bandwidth ? 100 mhz sampling rate ? excellent hold mode distortion -66 db @ 50 msps (f in = 25 mhz) -58 db @ 100 msps (f in = 50 mhz) ? track mode slew rate: 700 v/ m s ? low power: 120 mw differential mode 75 mw single-ended mode ? single +5 v supply ? internal +2.5 v reference block diagram general description the SPT9110 is a single-to-differential track-and-hold ampli- fier. it can be operated as a single-end tha only or, in full configuration, as a single-to-differential tha. an internal reference provides the common-mode voltage for the single- to-differential output stage. the tha, inverter and reference have separate power supply pins so each can be optionally powered up and used. this device provides an analog designer with a low cost single-to-differential tha amplifier for interfacing differential and single-ended adcs. the SPT9110 is offered in a 28-lead soic package in the industrial temperature range. signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 1x 1x c h old clk nclk analog in (v in ) +2.5 v reference ref out out+ out- - + ref in invert in a agnd av cc (ref) av cc (inv) av cc (tha) 1 k w 1 k w invert in b r2 r1
spt 2 11/12/98 SPT9110 electrical specifications av cc = +5.0 v, agnd = 0.0 v, output load = 1 k w and 10 pf, v in = 2.0 vp-p,internal reference, unless otherwise specified. test test SPT9110 parameters conditions level min typ max units dc performance gain d v in = 2.0 vp-p single ended out +25 c i 0.95 0.97 0.99 v/v full temperature v 0.96 v/v differential out +25 c i 1.80 1.93 2.00 v/v full temperature v 1.92 v/v offset v in = +2.5 v out+ +25 c i -100 50 +100 mv full temperature v 55 mv differential 1 +25 c, ref in=out+ cm i -15 5 15 mv full temperature v 10 mv output drive capacity 2 full temperature iv 1 10 ma output load at 10 pf full temperature v 1 k w analog input/output output voltage range full temperature vi 1.5 3.5 v input capacitance +25 cv 5pf input resistance +25 c i 100 140 k w reference voltage output i 2.35 2.45 2.55 v reference output current 3 +25 cv 100 m a reference voltage tempco full temperature v 75 ppm/ c clock inputs input type/logic family v differential pecl input bias current +25 ci 210 m a input low voltage (differential) +25 c i 3.3 3.5 v input high voltage (differential) +25 c i 3.9 4.1 v absolute maximum rating (beyond which damage may occur) 1 note 1: operation at any absolute maximum ratings is not implied. see electrical specifications for proper nominal applied conditions in typical application. note 2: outputs are short circuit protected. output currents 2 continuous output current ................................. 15 ma temperature operating temperature .............................. -40 to +85 c junction temperature ......................................... +150 c lead, soldering (10 seconds) ............................. +220 c storage ..................................................... -65 to +150 c supply voltages av cc supplies ............................................. -0.5 to +6 v input voltages analog input voltage .................................... -0.5 to +6 v clk, nclk input .......................................... -0.5 to +6 v ref in ............................................................ -0.5 to +6 v 1 differential offset is specified with ref in equal to the common mode output voltage of out+ and so includes the offset error o f the inverter only. 2 this part is intended to drive a high impedance load. ac performance is degraded at 10 ma. see the typical performance graphs. 3 ref out has a typical output impedance of 1 k w and should be buffered for driving loads other than ref in.
spt 3 11/12/98 SPT9110 electrical specifications av cc = +5.0 v, agnd = 0.0 v, output load = 1 k w and 10 pf, v in = 2.0 vp-p,internal reference, unless otherwise specified. test test SPT9110 parameters conditions level min typ max units track mode dynamics bandwidth (-3 db) +25 c single ended out v 220 mhz differential out v 140 mhz slew rate 2.0 vp-p output step +25 c single ended out 20 pf load iv 580 v/ m s differential out 7 20 pf load iv 800 v/ m s input rms spectral noise single ended v 3.5 nv/ hz differential v 13.0 nv/ hz track-to-hold switching aperture delay +25 c v 250 ps aperture jitter +25 c v <1 ps rms pedestal offset +25 civ 12 mv full temperature v 12 mv hold mode dynamics 4 (v in = 1 vp-p) worst harmonic 5 mhz, 50 msps, single-ended t a = +25 c iv -64 -68 db t a = -40 c to +85 c v -64 db worst harmonic 5 mhz, 50 msps, differential t a = +25 c iv -61 -65 db t a = -40 c to +85 c v -63 db worst harmonic 25 mhz, 50 msps, single-ended t a = +25 c v -66 db t a = -40 c to +85 c v -63 db worst harmonic 25 mhz, 50 msps, differential t a = +25 c v -64 db t a = -40 c to +85 c v -60 db worst harmonic 50 mhz, 100 msps, single-ended t a = +25 c iv -54 -58 db t a = -40 c to +85 c v -54 db worst harmonic 50 mhz, 100 msps, differential t a = +25 c iv -50 -54 db t a = -40 c to +85 c v -50 db sampling bandwidth 5 (-3 db) +25 c v 400 mhz v in = 2.0 vp-p hold noise 6 (rms) +25 c v 300 x t h mv/s droop rate, v in = +2.5 v +25 civ 40 mv/ m s full temperature iv 80 mv/ m s feedthrough rejection (50 mhz) full temperature v -65 db v in = 2 vp-p 4. for hold times longer than 50 ns, the input common mode voltage may affect the hold mode distortion. (this is due to nonlinea r droop that varies with vcm.) for optimal performance, spt recommends that the held output signal be used within 50 ns of the application of the hold signal. 5. sampling bandwidth is defined as the -3 db frequency response of the input sampler to the hold capacitor when operating in t he sampling mode. it is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier. 6. hold mode noise is proportional to the length of time a signal is held. this value must be combined with the track mode nois e to obtain total noise. 7. optimized for hold mode performance and low power.
spt 4 11/12/98 SPT9110 test level codes all electrical characteristics are subject to the following conditions: all parameters having min/ max specifications are guaranteed. the test level column indicates the specific device test- ing actually performed during production and quality assurance inspection. any blank sec- tion in the data column indicates that the speci- fication is not tested at the specified condition. test level i ii iii iv v vi test procedure 100% production tested at the specified temperature. 100% production tested at t a = +25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = +25 c. parameter is guaranteed over specified temperature range. electrical specifications av cc = +5.0 v, agnd = 0.0 v, r load = 1 k w and 10 pf, v in = 2.0 vp-p, internal reference, unless otherwise specified. test test SPT9110 parameters conditions level min typ max units hold-to-track switching 8 acquisition time to 0.1% +25 c v 3.5 ns 1 v output step acquisition time to 0.025% +25 c v 4.0 ns 1 v output step power supplies supply voltage iv 4.75 5 5.25 v supply current single ended output mode 9i 15 20 ma differential output mode i 24 30 ma power dissipation single ended output mode 9i 75 100 mw differential output mode i 120 150 mw power supply rejection ratio +25 c v 44 db single-ended output d v cc = 0.5 v p-p 8. measured at the hold capacitor. 9. inverter powered down.
spt 5 11/12/98 SPT9110 timing specification definitions acquisition time this is the time it takes the SPT9110 to acquire the analog signal at the internal hold capacitor when it makes a transition from hold mode to track mode. (see figure 1.) the acquisition time is measured from the 50% input clock transition point to the point when the signal is within a specified error band at the internal hold capacitor (ahead of the output amplifier). it does not include the delay and settling time of the output amplifier. because the signal is internally acquired and settled at the hold capacitor before the output voltage has settled, the sampler can be put in hold mode before the output has settled. track-to-hold settling time the time required for the output to settle to within 4 mv of its final value. aperture delay the aperture delay time is the interval between the leading edge transition of the clock input and the instant when the input signal was equal to the held value. it is the difference in time between the digital hold switch delay and the analog signal propagation time. figure 1 - timing diatram acquisition time aperature delay track-to-hold settling hold track hold clk nclk output input observed at hold capacitor observed at amplifier output
spt 6 11/12/98 SPT9110 general description the SPT9110 is a low cost 100 msps track-and-hold ampli- fier with single ended (75 mw) or differential output (120 mw). it consists of three components. the first is a single-ended track-and-hold amplifier (tha) with a 1.5 to 3.5 v input range and pecl clock inputs. the second is an inverting op amp with gain of -1 to provide the differential output (out-). the third component is a 2.5 v bandgap reference for the inverter. partitioned power supply management three separate +5 v supply connections power the tha, inverting the op amp and bandgap reference. unused com- ponents can be powered off to minimize power dissipation. the single-ended mode requires use of only the tha and output on the out+ pin. in this mode the reference and inverter may be powered down. the differential mode requires use of all three components (unless an external reference is supplied). the output is measured between out+ and out- in this mode. figure 2 - typical output response to step input 500 mv/ division 1.0 ns/division out+ out- out+ inp ut out-
spt 7 11/12/98 SPT9110 figure 3 - typical interface circuit (single-ended operational design) n/c n/c 5 6 7 8 SPT9110 a+5v 1 2 3 4 q0 gnd do v cc mc100elt22 d1 q1 gnd(ref) ref out ref in gnd(tha) gnd(sub) gnd(cap) analog in gnd(tha) gnd(tha) gnd(tha) gnd(tha) av cc (ref) gnd(sub) gnd(inv) clk av cc (tha) out+ out- inv a inv b av cc (inv) av cc (esd) av cc (tha) av cc (tha) av cc (tha) av cc (tha) av cc (inv) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 10 300 50 50 1 f 0.01 f a+5v 0.1 f ttl clock (sample clock, up to 100 mhz) (+3.0 v) a+5v a+5v out 4.7 f 0.01 f 0.01 f a+5v 0.01 f 4.7 f 0.1 f (+2.5 v) xuf (dependent on frequency) 50 - + op191 2 3 7 4 6 0.01 f (optional level-shift circuit) + + + 4.7 f + 22 (ttl to pecl translator) 22 analog in clk q0 q1 notes: 1. input signal is typically at a +2.5 v offset. the optional level-shift circuit may be eliminated if driving from a source that already provides for this offset. 2. the device may be operated from -5 v supply on gnd pins and 0 v on av cc pins. all input and output pins will be shifted by -5 v. the use of an ecl level may be used to drive the clock inputs. 3. v cc (esd) is the high voltage for the esd protection diodes and must be connected in all applications. note: it should be tied to v cc (tha), not to v cc (inv). n/c n/c n/c n/c 0.01 f figure 4 - typical interface circuit (differential operational design) 5 6 7 8 SPT9110 a+5v 1 2 3 4 q0 gnd do v cc mc100elt22 d1 q1 gnd(ref) ref out ref in gnd(tha) gnd(sub) gnd(cap) analog in gnd(tha) gnd(tha) gnd(tha) gnd(tha) av cc (ref) gnd(sub) gnd(inv) clk av cc (tha) out+ out- inv a inv b av cc (inv) av cc (esd) av cc (tha) av cc (tha) av cc (tha) av cc (tha) av cc (inv) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 10 300 50 50 1 f 0.01 f a+5v 0.1 f ttl clock (sample clock, up to 100 mhz) (+3.0 v) a+5v a+5v out+ out- 4.7 f 0.01 f 4.7 f 0.01 f a+5v 0.01 f 4.7 f 4.7 f 0.01 f 0.1 f (+2.5 v) xuf (dependent on frequency) 50 - + op191 2 3 7 4 6 0.01 f (optional level-shift circuit) (differential output) + + + + + 22 (ttl to pecl translator) 22 22 analog in clk q0 q1 notes: 1. input signal is typically at a +2.5 v offset. the optional level-shift circuit may be eliminated if driving from a source that already provides for this offset. 2. the device may be operated from -5 v supply on gnd pins and 0 v on av cc pins. all input and output pins will be shifted by -5 v. the use of an ecl level may be used to drive the clock inputs. 3. v cc (esd) is the high voltage for the esd protection diodes and must be connected in all applications. note: it should be tied to v cc (tha), not to v cc (inv).
spt 8 11/12/98 SPT9110 typical performance characteristics single-ended (out+) hold mode distortion vs. sample rate -40 -45 -50 -55 -60 -65 50 70 90 110 130 150 170 190 sample rate (msps) worst harmonic (db) input = 50 mhz input = 25 mhz track mode bandwidth 0 40 80 120 160 200 input frequency (mhz) db out- out+ -6 -4 -2 0 +2 reference output voltage vs. temperature 2.46 2.47 2.48 2.49 2.5 temperature (?) volts -50 0 +50 100 slew rate vs. temperature v out = 2 v p-p 300 500 700 900 -50 0 50 100 temperature (?) v/s out+ out- differential track mode distortion vs. input frequency v in = 1 v p-p -50 -55 -60 -65 -70 -75 0 5 10 15 20 25 30 35 40 input frequency (mhz) worst harmonic (db) single ended track mode distortion vs. input frequency v in = 1v p-p -35 -40 -45 -50 -55 -60 -65 -70 -75 10 20 30 40 50 60 70 80 input frequency (mhz) worst harmonics (db) out+ out-
spt 9 11/12/98 SPT9110 typical performance characteristics track mode distortion vs. ac coupled resistive load f in = 40 mhz, 1 v p-p c load = 10 pf -35 -40 -45 -50 -55 -60 -65 -70 0 250 500 750 1000 1250 1500 1750 2000 r load (ohms) worst harmonic (db) out+ tha r load 0.01 f c load hold mode distortion vs. temperature f in = 5 mhz, f s = 50 msps ?c worst harmonic (db) -66 -68 -70 -72 -74 -76 -78 -40 -20 0 20 40 60 80 100 out+ out- hold mode distortion vs. temperature f in = 25 mhz, f s = 50 msps -50 -55 -60 -65 -70 -40 -20 0 20 40 60 80 100 ? worst harmonic (db) out+ out- hold mode distortion vs. temperature f in = 50 mhz, f s = 100 msps -40 -45 -50 -55 -60 -65 -40 -20 0 20 40 60 80 100 ? worst harmonic (db) dc parameters vs. temperature (v in = 2.5 v) -40 -20 0 20 40 60 80 -50 0 50 100 temperature (?c) mv (mv/s for droop) droop pedestal offset differential offset single-ended offset
spt 10 11/12/98 SPT9110 inches millimeters symbol min max min max a 0.696 0.712 17.68 18.08 b 0.004 0.012 0.10 0.30 c .050 typ 0.00 1.27 d 0.014 0.019 0.36 0.48 e 0.009 0.012 0.23 0.30 f 0.080 0.100 2.03 2.54 g 0.016 0.050 0.41 1.27 h 0.394 0.419 10.01 10.64 i 0.291 0.299 7.39 7.59 1 28 a b cd e f g i h h package outline 28-lead soic
spt 11 11/12/98 SPT9110 pin assignments pin functions name function analog in single-ended analog input to the tha invert ina inverting input a to inverting amplifier resistor r1 invert inb inverting input b to inverting amplifier resistor r2 out+ single-ended output of the tha out- output from the inverting amplifier clk noninverting differential pecl clock input nclk inverting differential pecl clock input ref in common-mode reference for the inverting amplifier ref out internal +2.5 v reference output av cc (tha) track-and-hold analog +5 v supply av cc (inv) inverter +5 v supply av cc (ref) internal reference +5 v supply av cc (esd) +5 v supply for esd protection diodes agnd (tha) track-and-hold analog ground agnd (cap) hold capacitor analog ground agnd (sub) substrate analog ground agnd (inv) inverter analog ground agnd (ref) internal reference analog ground part number temperature range package type SPT9110sis -40 to +85 c 28l soic ordering information signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited . warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, ca n be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty. agnd (tha) agnd (tha) analog in agnd (sub) agnd (tha) agnd (cap) agnd (tha) agnd (tha) ref in ref out av cc (ref) agnd (ref) agnd (sub) agnd (inv) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 out+ av cc (tha) av cc (inv) invert inb out- av cc (inv) invert ina av cc (tha) av cc (tha) av cc (tha) av cc (tha) nclk clk av cc (esd)

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